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Espressif Systems /ESP32-S3 /SENS /SAR_COCPU_STATE

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Interpret as SAR_COCPU_STATE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SAR_COCPU_DBG_TRIGGER)SAR_COCPU_DBG_TRIGGER 0 (SAR_COCPU_CLK_EN_ST)SAR_COCPU_CLK_EN_ST 0 (SAR_COCPU_RESET_N)SAR_COCPU_RESET_N 0 (SAR_COCPU_EOI)SAR_COCPU_EOI 0 (SAR_COCPU_TRAP)SAR_COCPU_TRAP 0 (SAR_COCPU_EBREAK)SAR_COCPU_EBREAK

Description

get cocpu status

Fields

SAR_COCPU_DBG_TRIGGER

trigger cocpu debug registers
SAR_COCPU_CLK_EN_ST

check cocpu whether clk on
SAR_COCPU_RESET_N

check cocpu whether in reset state
SAR_COCPU_EOI

check cocpu whether in interrupt state
SAR_COCPU_TRAP

check cocpu whether in trap state
SAR_COCPU_EBREAK

check cocpu whether in ebreak

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data